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VLSI-SoC: Design Trends
28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers
- Conference proceedings
- © 2021
- Andrea Calimera ORCID: https://orcid.org/0000-0001-5881-3811 0 ,
- Pierre-Emmanuel Gaillardon ORCID: https://orcid.org/0000-0003-3634-3999 1 ,
- Kunal Korgaonkar ORCID: https://orcid.org/0000-0002-9078-2944 2 ,
- Shahar Kvatinsky ORCID: https://orcid.org/0000-0001-7277-7271 3 ,
- Ricardo Reis ORCID: https://orcid.org/0000-0001-5781-5858 4
Politecnico di Torino, Turin, Italy
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University of Utah, Salt Lake City, USA
Technion – israel institute of technology, haifa, israel, universidade federal do rio grande do sul, porto alegre, brazil.
Part of the book series: IFIP Advances in Information and Communication Technology (IFIPAICT, volume 621)
Included in the following conference series:
- VLSI-SoC: IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip
Conference proceedings info: VLSI-SoC 2020.
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About this book
The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs.
*The conference was held virtually.
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ITRS 2028—International Roadmap of Semiconductors
- artificial intelligence
- communication systems
- computer hardware
- computer-aided design
- distributed computer systems
- distributed systems
- embedded systems
- field programmable gate array
- integrated circuits
- microprocessor chips
- network protocols
- parallel processing systems
- signal processing
- telecommunication systems
- vlsi circuits
Table of contents (16 papers)
Front matter, low-power high-speed adcs for adc-based wireline receivers in 22 nm fdsoi.
- David Cordova, Wim Cops, Yann Deval, François Rivet, Herve Lapuyade, Nicolas Nodenot et al.
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector
- Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring
- Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation
- Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta et al.
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform
- Alessandro Veronesi, Davide Bertozzi, Milos Krstic
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays
- Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
Learning Based Timing Closure on Relative Timed Design
- Tannu Sharma, Sumanth Kolluru, Kenneth S. Stevens
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication
- Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
From Informal Specifications to an ABV Framework for Industrial Firmware Verification
- Samuele Germiniani, Moreno Bragaglio, Graziano Pravadelli
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs
- Josie Esteban Rodriguez Condia, Matteo Sonza Reorda
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique
- Jonas Gava, Ricardo Reis, Luciano Ost
SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption
- Yinghua Hu, Kaixin Yang, Shahin Nazarian, Pierluigi Nuzzo
3D Nanofabric : Layout Challenges and Solutions for Ultra-scaled Logic Designs
- Edouard Giacomin, Juergen Boemmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
- Arnaud Poittevin, Chhandak Mukherjee, Ian O’Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng et al.
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics
- Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung-Kyu Lim, Arijit Raychowdhury
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory
- Adi Eliahu, Rotem Ben-Hur, Ronny Ronen, Shahar Kvatinsky
Back Matter
Other volumes, editors and affiliations.
Andrea Calimera
Pierre-Emmanuel Gaillardon
Kunal Korgaonkar, Shahar Kvatinsky
Ricardo Reis
Bibliographic Information
Book Title : VLSI-SoC: Design Trends
Book Subtitle : 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6–9, 2020, Revised and Extended Selected Papers
Editors : Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis
Series Title : IFIP Advances in Information and Communication Technology
DOI : https://doi.org/10.1007/978-3-030-81641-4
Publisher : Springer Cham
eBook Packages : Computer Science , Computer Science (R0)
Copyright Information : IFIP International Federation for Information Processing 2021
Hardcover ISBN : 978-3-030-81640-7 Published: 15 July 2021
Softcover ISBN : 978-3-030-81643-8 Published: 15 July 2022
eBook ISBN : 978-3-030-81641-4 Published: 14 July 2021
Series ISSN : 1868-4238
Series E-ISSN : 1868-422X
Edition Number : 1
Number of Pages : XVIII, 364
Number of Illustrations : 70 b/w illustrations, 139 illustrations in colour
Topics : Computer Systems Organization and Communication Networks , Control Structures and Microprogramming , Input/Output and Data Communications , Information Systems Applications (incl. Internet)
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IMAGES
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This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI...
the AI/ML automated approaches introduced in the past toward VLSI design and manufacturing. Moreover, we discuss the future scope of AI/ML applications to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.
Abstract: The current research in VLSI explores emerging trends and novel ideas and concepts covering a broad range of topics in the area of VLSI: from VLSI circuits, systems, and design methods, to system-level design and systemon- chip issues, to bringing VLSI methods to new areas and technologies such as nano and molecular devices, MEMS, and ...
Explore the latest full-text research PDFs, articles, conference papers, preprints and more on VLSI DESIGN. Find methods information, sources, references or conduct a literature review on...
A high-productivity digital VLSI flow for designing complex SoCs is presented. The flow includes high-level synthesis tools, an object-oriented library of synthesizable SystemC and C++ components, and a modular VLSI physical design approach based on fine-grained globally asynchronous locally synchronous (GALS) clocking.
In this paper, we review the recent advances of SOI technology for digital CMOS very-large-scale-integration (VLSI) applications. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. Section II discusses the SOI device structures and the floating-body effect in partially depleted devices.
This research article provides an insight about the important challenges involved in the low power analog system design using advanced CMOS VLSI approach.
To increase the battery life of portable devices, leakage and dynamic power reduction is emerging as a primary goal of the VLSI circuit design. This paper provides an insight about the various methodologies, strategies and power management techniques to be used for the design of low power circuit based systems.
The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies.
This paper gives a brief review of the AI/ML algorithms and applications that could be used in VLSI design technology.